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MC34071,2,4,A MC33071,2,4,A Single Supply 3.0 V to 44 V Operational Amplifiers
Quality bipolar fabrication with innovative design concepts are employed for the MC33071/72/74, MC34071/72/74 series of monolithic operational amplifiers. This series of operational amplifiers offer 4.5 MHz of gain bandwidth product, 13 V/ms slew rate and fast settling time without the use of JFET device technology. Although this series can be operated from split supplies, it is particularly suited for single supply operation, since the common mode input voltage range includes ground potential (VEE). With a Darlington input stage, this series exhibits high input resistance, low input offset voltage and high gain. The all NPN output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink AC frequency response. The MC33071/72/74, MC34071/72/74 series of devices are available in standard or prime performance (A Suffix) grades and are specified over the commercial, industrial/vehicular or military temperature ranges. The complete series of single, dual and quad operational amplifiers are available in plastic DIP, SOIC and TSSOP surface mount packages.
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8 1
PDIP-8 P SUFFIX CASE 626
8 1
SOIC-8 D SUFFIX CASE 751
14 1
PDIP-14 P SUFFIX CASE 646
* * * * * * * * * * * * * *
Wide Bandwidth: 4.5 MHz High Slew Rate: 13 V/ms Fast Settling Time: 1.1 ms to 0.1% Wide Single Supply Operation: 3.0 V to 44 V Wide Input Common Mode Voltage Range: Includes Ground (VEE) Low Input Offset Voltage: 3.0 mV Maximum (A Suffix) Large Output Voltage Swing: -14.7 V to +14 V (with 15 V Supplies) Large Capacitance Drive Capability: 0 pF to 10,000 pF Low Total Harmonic Distortion: 0.02% Excellent Phase Margin: 60 Excellent Gain Margin: 12 dB Output Short Circuit Protection ESD Diodes/Clamps Provide Input Protection for Dual and Quad Pb-Free Packages are Available
14 1
SOIC-14 D SUFFIX CASE 751A
14 1
TSSOP-14 DTB SUFFIX CASE 948G
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 18 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2004
1
April, 2004 - Rev. 8
Publication Order Number: MC34071/D
MC34071,2,4,A MC33071,2,4,A
PIN CONNECTIONS
CASE 626/CASE 751 Offset Null Inputs VEE
1 2 3 4 - + 8 7 6 5
CASE 646/CASE 751A/CASE 948G
NC VCC Output Offset Null
Output 1 Inputs 1 VCC Inputs 2
1 2 3 4 5 6 7 + - - + 1 4 - +
14 13
Output 4 Inputs 4
12 11
VEE Inputs 3 Output 3
(Single, Top View) Output 1 Inputs 1 VEE
1 2 3 4 - + - + 8 7 6 5
2
3
VCC Output 2 Inputs 2
+ -
10 9 8
Output 2
(Quad, Top View)
(Dual, Top View)
VCC Q3 Q1 Q2 R1 Bias - Inputs + C2 D3 Q19 Base Current Cancellation Q13 Q12 D1 R5 R3 R4 Current Limit Q14 Q15 Q16 Q8 Q9 Q10 C1 R2 Q11 Q4 Q5 Q6 Q7 Q17 D2 R6 R7 Output R8 Q18
VEE/GND Offset Null (MC33071, MC34071 only)
Figure 1. Representative Schematic Diagram (Each Amplifier) MAXIMUM RATINGS
Rating Supply Voltage (from VEE to VCC) Input Differential Voltage Range Input Voltage Range Output Short Circuit Duration (Note 2) Operating Junction Temperature Storage Temperature Range Symbol VS VIDR VIR tSC TJ Tstg Value +44 (Note 1) (Note 1) Indefinite +150 -60 to +150 Unit V V V Sec C C
1. Either or both input voltages should not exceed the magnitude of VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).
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MC34071,2,4,A MC33071,2,4,A
ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, RL = connected to ground, unless otherwise noted. See Note 3 for
TA = Tlow to Thigh) A Suffix Characteristics Input Offset Voltage (RS = 100 W, VCM = 0 V, VO = 0 V) VCC = +15 V, VEE = -15 V, TA = +25C VCC = +5.0 V, VEE = 0 V, TA = +25C VCC = +15 V, VEE = -15 V, TA = Tlow to Thigh Average Temperature Coefficient of Input Offset Voltage RS = 10 W, VCM = 0 V, VO = 0 V, TA = Tlow to Thigh Input Bias Current (VCM = 0 V, VO = 0 V) TA = +25C TA = Tlow to Thigh Input Offset Current (VCM = 0 V, VO = 0V) TA = +25C TA = Tlow to Thigh Input Common Mode Voltage Range TA = +25C TA = Tlow to Thigh Large Signal Voltage Gain (VO = 10 V, RL = 2.0 kW) TA = +25C TA = Tlow to Thigh Output Voltage Swing (VID = 1.0 V) VCC = +5.0 V, VEE = 0 V, RL = 2.0 kW, TA = +25C VCC = +15 V, VEE = -15 V, RL = 10 kW, TA = +25C VCC = +15 V, VEE = -15 V, RL = 2.0 kW, TA = Tlow to Thigh VCC = +5.0 V, VEE = 0 V, RL = 2.0 kW, TA = +25C VCC = +15 V, VEE = -15 V, RL = 10 kW, TA = +25C VCC = +15 V, VEE = -15 V, RL = 2.0 kW, TA = Tlow to Thigh Output Short Circuit Current (VID = 1.0 V, VO = 0 V, TA = 25C) Source Sink Common Mode Rejection RS 10 kW, VCM = VICR, TA = 25C Power Supply Rejection (RS = 100 W) VCC/VEE = +16.5 V/-16.5 V to +13.5 V/-13.5 V, TA = 25C Power Supply Current (Per Amplifier, No Load) VCC = +5.0 V, VEE = 0 V, VO = +2.5 V, TA = +25C VCC = +15 V, VEE = -15 V, VO = 0 V, TA = +25C VCC = +15 V, VEE = -15 V, VO = 0 V, TA = Tlow to Thigh 3. Tlow = -40C for MC33071, 2, 4, /A = 0C for MC34071, 2, 4, /A = -40C for MC34072, 4/V Thigh Symbol VIO Min - - - - Typ 0.5 0.5 - 10 Max 3.0 3.0 5.0 - Min - - - - Non-Suffix Typ 1.0 1.5 - 10 Max 5.0 5.0 7.0 - mV/C Unit mV
DVIO/DT
IIB - - IIO - - VICR VEE to (VCC -1.8) VEE to (VCC -2.2) AVOL 50 25 VOH 3.7 13.6 13.4 VOL 4.0 14 - 0.1 -14.7 - - - - 0.3 -14.3 -13.5 3.7 13.6 13.4 - - - 4.0 14 - 0.1 -14.7 - - - - 0.3 -14.3 -13.5 100 - - - 25 20 100 - - - VEE to (VCC -1.8) VEE to (VCC -2.2) 6.0 - 50 300 - - 6.0 - 75 300 100 - 500 700 - - 100 - 500 700
nA
nA
V
V/mV
V
- - -
V
ISC 10 20 CMR PSR 80 80 30 30 97 97 - - - - 10 20 70 70 30 30 97 97 - - - -
mA
dB dB
ID - - - 1.6 1.9 - 2.0 2.5 2.8 - - - 1.6 1.9 - 2.0 2.5 2.8
mA
= +85C for MC33071, 2, 4, /A = +70C for MC34071, 2, 4, /A = +125C for MC34072, 4/V
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MC34071,2,4,A MC33071,2,4,A
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, RL = connected to ground. TA = +25C, unless otherwise noted.)
A Suffix Characteristics Slew Rate (Vin = -10 V to +10 V, RL = 2.0 kW, CL = 500 pF) AV = +1.0 AV = -1.0 Setting Time (10 V Step, AV = -1.0) To 0.1% (+1/2 LSB of 9-Bits) To 0.01% (+1/2 LSB of 12-Bits) Gain Bandwidth Product (f = 100 kHz) Power Bandwidth AV = +1.0, RL = 2.0 kW, VO = 20 Vpp, THD = 5.0% Phase margin RL = 2.0 kW RL = 2.0 kW, CL = 300 pF Gain Margin RL = 2.0 kW RL = 2.0 kW, CL = 300 pF Equivalent Input Noise Voltage RS = 100 W, f = 1.0 kHz Equivalent Input Noise Current f = 1.0 kHz Differential Input Resistance VCM = 0 V Differential Input Capacitance VCM = 0 V Total Harmonic Distortion AV = +10, RL = 2.0 kW, 2.0 Vpp VO 20 Vpp, f = 10 kHz Channel Separation (f = 10 kHz) Open Loop Output Impedance (f = 1.0 MHz) Symbol SR 8.0 - ts - - GBW BW fm - - Am - - en in Rin Cin THD - |ZO| - - - - - - - 12 4.0 32 0.22 150 2.5 0.02 120 30 - - - - - - - - - - - - - - - - - - 12 4.0 32 0.22 150 2.5 0.02 120 30 - - - - - - - - - nV/ Hz pA/ Hz MW pF % dB W 60 40 - - - - 60 40 - - dB 3.5 - 1.1 2.2 4.5 160 - - - - - - 3.5 - 1.1 2.2 4.5 160 - - - - MHz kHz Deg 10 13 - - 8.0 - 10 13 - - ms Min Typ Max Min Non-Suffix Typ Max Unit V/ms
Single Supply
3.0 V to 44 V VCC 1 2 3 4 VEE VEE VCC
Split Supplies
VCC+|VEE|44 V VCC 2 1 3 2 3 4 VEE VEE Offset nulling range is approximately 80 mV with a 10 k potentiometer (MC33071, MC34071 only). - + 4 10 k 5 VCC 7 6 1
Figure 2. Power Supply Configurations
Figure 3. Offset Null Circuit
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MC34071,2,4,A MC33071,2,4,A
P D , MAXIMUM POWER DISSIPATION (mW) 2400 2000 1600 SOIC-14 Pkg 1200 800 400 0 -55 -40 -20 SOIC-8 Pkg 8 & 14 Pin Plastic Pkg V V IO , INPUT OFFSET VOLTAGE (mV) 4.0 2.0 0 -2.0 -4.0 -55 -25 0 25 50 75 100 125 VCC = +15 V VEE = -15 V VCM = 0
0
20
40
60
80
100 120 140 160
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 4. Maximum Power Dissipation versus Temperature for Package Types
V ICR , INPUT COMMON MODE VOLTAGE RANGE (V) I IB, INPUT BIAS CURRENT (NORMALIZED)
Figure 5. Input Offset Voltage versus Temperature for Representative Units
VCC VCC VCC -0.8 VCC -1.6 VCC -2.4 VEE +0.01 VEE VEE -55 -25 0 25 50 75 100 125 VCC/VEE = +1.5 V/ -1.5 V to +22 V/ -22 V
1.3 1.2 1.1 1.0 0.9 0.8 0.7 -55 VCC = +15 V VEE = -15 V VCM = 0
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 6. Input Common Mode Voltage Range versus Temperature
Figure 7. Normalized Input Bias Current versus Temperature
I IB, INPUT BIAS CURRENT (NORMALIZED)
1.4 VO, OUTPUT VOLTAGE SWING (Vpp ) VCC = +15 V VEE = -15 V TA = 25C
50 40 30 RL = 10 k 20 10 0 -12 -8.0 -4.0 0 4.0 8.0 12 0 5.0 10 15 20 25 VIC, INPUT COMMON MODE VOLTAGE (V) VCC, |VEE|, SUPPLY VOLTAGE (V) RL = 2.0 k RL Connected to Ground TA = 25C
1.2
1.0
0.8
0.6
Figure 8. Normalized Input Bias Current versus Input Common Mode Voltage
Figure 9. Split Supply Output Voltage Swing versus Supply Voltage
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MC34071,2,4,A MC33071,2,4,A
Vsat , OUTPUT SATURATION VOLTAGE (V) Vsat , OUTPUT SATURATION VOLTAGE (V) VCC VCC VCC -1.0 Source VCC -2.0 VEE +2.0 VEE +1.0 VEE Sink VEE 0 5.0 10 IL, LOAD CURRENT ( mA) 15 VCC/VEE = +5.0 V/ -5.0 V to +22 V/ -22 V TA = 25C VCC VCC-2.0 VCC-4.0 0.2 0.1 GND 0 100 1.0 k 10 k 100 k VCC VCC = +15 V RL = GND TA = 25C
20
RL, LOAD RESISTANCE TO GROUND (W)
Figure 10. Single Supply Output Saturation versus Load Resistance to VCC
Figure 11. Split Supply Output Saturation versus Load Current
Vsat , OUTPUT SATURATION VOLTAGE (V)
0 I SC, OUTPUT CURRENT (mA) VCC -0.4 -0.8 2.0 1.0 GND 100 1.0 k 10 k 100 k
60 50 40 Source 30 20 10 0 -55 VCC = +15 V VEE = -15 V RL 0.1 W DVin = 1.0 V -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C)
Sink
VCC = +15 V RL to VCC TA = 25C
RL, LOAD RESISTANCE TO VCC (W)
Figure 12. Single Supply Output Saturation versus Load Resistance to Ground
Figure 13. Output Short Circuit Current versus Temperature
50 VO, OUTPUT VOLTAGE SWING (Vpp ) Z O, OUTPUT IMPEDANCE ( ) 40 30 20 AV = 1000 10 0 1.0 k AV = 100 AV = 10 AV = 1.0 VCC = +15 V VEE = -15 V VCM = 0 VO = 0 DIO = 0.5 mA TA = 25C
28 24 20 16 12 8.0 4.0 0 3.0 k VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k THD 1.0% TA = 25C
10 k
100 f, FREQUENCY (Hz)
1.0 M
10 M
10 k
30 k 100 k 300 k f, FREQUENCY (Hz)
1.0 M
3.0 M
Figure 14. Output Impedance versus Frequency
Figure 15. Output Voltage Swing versus Frequency
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MC34071,2,4,A MC33071,2,4,A
THD, TOTAL HARMONIC DISTORTION (%) THD, TOTAL HARMONIC DISTORTION (%) 0.4 AV = 1000 0.3 VCC = +15 V VEE = -15 V VO = 2.0 Vpp RL = 2.0 k TA = 25C 4.0 VCC = +15 V VEE = -15 V RL = 2.0 k TA = 25C
3.0
AV = 1000
0.2 AV = 100 0.1 AV = 10 0 10 100 1.0 k f, FREQUENCY (Hz)
2.0 AV = 100 1.0 AV = 10 AV = 1.0 0 0 4.0 8.0 12 16 20 VO, OUTPUT VOLTAGE SWING (Vpp)
AV = 1.0 10 k 100 k
Figure 16. Total Harmonic Distortion versus Frequency
Figure 17. Total Harmonic Distortion versus Output Voltage Swing
AVOL , OPEN LOOP VOLTAGE GAIN (dB)
AVOL , OPEN LOOP VOLTAGE GAIN (dB)
116 112 108 104 100 96 -55 VCC = +15 V VEE = -15 V VO= -10 V to +10 V RL = 10 k f 10Hz
100 0 80 Phase 60 40 20 0 1.0 VCC = +15 V VEE = -15 V VO = 0 V RL = 2.0 k TA = 25C 10 100 1.0 k 10 k 100 k 1.0 M 10 M f, FREQUENCY (Hz) Phase Margin = 60 90 135 180 100 M Gain 45 , EXCESS PHASE (DEGREES) 125
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
Figure 18. Open Loop Voltage Gain versus Temperature
Figure 19. Open Loop Voltage Gain and Phase versus Frequency
AVOL , OPEN LOOP VOLTAGE GAIN (dB)
20 10 0 -10
GBW, GAIN BANDWIDTH PRODUCT (NORMALIED)
1
1.15 1.1 1.05 1.0 0.95 0.9 0.85 -55 VCC = +15 V VEE = -15 V RL = 2.0 k
Gain Margin = 12 dB
120 140
1. Phase RL = 2.0 k 2. Phase RL = 2.0 k, CL = 300 pF -20 3. Gain RL = 2.0 k 4. Gain RL = 2.0 k, CL = 300 pF -30 VCC = +15 V VEE = 15 V VO = 0 V TA = 25C -40 1.0 2.0 3.0 5.0 7.0
3 4 2 10 20
160 180
30
, EXCESS PHASE (DEGREES)
Phase Margin = 60
100
-25
0
25
50
75
100
f, FREQUENCY (MHz)
TA, AMBIENT TEMPERATURE (C)
Figure 20. Open Loop Voltage Gain and Phase versus Frequency
Figure 21. Normalized Gain Bandwidth Product versus Temperature
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MC34071,2,4,A MC33071,2,4,A
100 m , PHASE MARGIN (DEGREES) 80 60 40 20 0 VCC = +15 V VEE = -15 V RL = 2.0 k VO = -10 V to +10 V TA = 25C 70 60 50 40 30 20 10 0 10 100 1.0 k 10 k VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k to R VO = -10 V to +10 V TA = 25C
PERCENT OVERSHOOT
10
100
1.0 k
10 k
CL, LOAD CAPACITANCE (pF)
CL, LOAD CAPACITANCE (pF)
Figure 22. Percent Overshoot versus Load Capacitance
Figure 23. Phase Margin versus Load Capacitance
14 12 A m , GAIN MARGIN (dB) 10 8.0 6.0 4.0 2.0 0 10 100 1.0 k 10 k CL, LOAD CAPACITANCE (pF) VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k to VO = -10 V to +10 V TA = 25C m , PHASE MARGIN (DEGREES)
80 CL = 10 pF 60 CL = 100 pF VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k to VO = -10 V to +10 V
40
20
CL = 1,000 pF
CL = 10,000 pF 0 -55 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (C)
Figure 24. Gain Margin versus Load Capacitance
Figure 25. Phase Margin versus Temperature
16 VCC = +15 V A m , GAIN MARGIN (dB) 12 VEE = -15 V AV = +1.0 RL = 2.0 k to VO = -10 V to +10 V A m , GAIN MARGIN (dB) CL = 10 pF
12 10 8.0 6.0
R2 R1
70 Gain
-
+
60 50
VO
8.0
CL = 100 pF CL = 10,000 pF
40 30 Phase 20 10 100 1.0 k 10 k 0 100 k
4.0 2.0 0
4.0
CL = 1,000 pF
0 -55
VCC = +15 V VEE = -15 V RT = R1 + R2 AV = +100 VO = 0 V TA = 25C 10
-25
0
25
50
75
100
125
1.0
TA, AMBIENT TEMPERATURE (C)
RT, DIFFERENTIAL SOURCE RESISTANCE (W)
Figure 26. Gain Margin versus Temperature
Figure 27. Phase Margin and Gain Margin versus Differential Source Resistance
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m , PHASE MARGIN (DEGREES)
MC34071,2,4,A MC33071,2,4,A
V O , OUTPUT VOLTAGE SWING FROM 0 V (V) 1.15 SR, SLEW RATE (NORMALIZED) 1.1 1.05 1.0 0.95 0.9 0.85 -55 VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k CL = 500 pF 10 1.0 mV 10 mV 5.0 1.0 mV VCC = +15 V VEE = -15 V AV = -1.0 TA = 25C Compensated Uncompensated 1.0 mV 10 mV 1.0 mV -10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
0
-5.0
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
ts, SETTLING TIME (ms)
Figure 28. Normalized Slew Rate versus Temperature
Figure 29. Output Settling Time
50 mV/DIV
5.0 V/DIV
0
VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k CL = 300 pF TA = 25C 2.0 ms/DIV
0
VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 k CL = 300 pF TA = 25C
1.0 ms/DIV
Figure 30. Small Signal Transient Response
Figure 31. Large Signal Transient Response
CMR, COMMON MODE REJECTION (dB)
100 80 60 40
DVCM
TA = 25C TA = -55C
VCC = +15 V VEE = -15 V VCM = 0 V DVCM = 1.5 V
PSR, POWER SUPPLY REJECTION (dB)
TA = 125C
100 80
DVCC
VCC = +15 V VEE = -15 V TA = 25C
- ADM
+
60 40 20
DVO DVEE
(DVCC = +1.5 V)
+
- ADM DVCM DVO
DVO
+PSR = 20 Log
DVO/ADM DVCC DVO/ADM DVEE
+PSR
20
CMR = 20 Log
x ADM
-PSR = 20 Log
0 0.1
1.0
10
100
1.0 k
10 k
100 k
1.0 M
10 M
0 0.1
-PSR (DVEE = +1.5 V) 1.0 k 10 k 100 k 1.0 M 10 M
1.0
10
100
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 32. Common Mode Rejection versus Frequency
Figure 33. Power Supply Rejection versus Frequency
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MC34071,2,4,A MC33071,2,4,A
PSR, POWER SUPPLY REJECTION (dB) 9.0 I CC , SUPPLY CURRENT (mA) 8.0 7.0 6.0 TA = 125C 5.0 4.0 0 5.0 10 15 20 25 VCC, |VEE|, SUPPLY VOLTAGE (V) TA = -55C 105 -PSR (DVEE = +1.5 V) 95 +PSR (DVCC = +1.5 V) 85
+PSR = 20 Log DVO/ADM DVCC DVO/ADM DVEE DVCC - ADM
+
VCC = +15 V VEE = -15 V
TA = 25C
75
-PSR = 20 Log
DVO DVEE
65 -55
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
Figure 34. Supply Current versus Supply Voltage
120 CHANNEL SEPARATION (dB) 100 80 60 40 20 0 10 20 30 50 70 100 200 300 f, FREQUENCY (kHz) VCC = +15 V VEE = -15 V TA = 25C 70 60 50 40 30 20 10 0 10
Figure 35. Power Supply Rejection versus Temperature
2.8 VCC = +15 V VEE = -15 V VCM = 0 TA = 25C Voltage 2.4 2.0 1.6 1.2 Current 0.8 0.4 100 1.0 k f, FREQUENCY (kHz) 10 k 0 100 k i n , INPUT NOISE CURRENT (pA Hz )
Figure 36. Channel Separation versus Frequency
e n , INPUT NOICE VOLTAGE ( nV Hz )
Figure 37. Input Noise versus Frequency
APPLICATIONS INFORMATION CIRCUIT DESCRIPTION/PERFORMANCE FEATURES Although the bandwidth, slew rate, and settling time of the MC34071 amplifier series are similar to op amp products utilizing JFET input devices, these amplifiers offer other additional distinct advantages as a result of the PNP transistor differential input stage and an all NPN transistor output stage. Since the input common mode voltage range of this input stage includes the VEE potential, single supply operation is feasible to as low as 3.0 V with the common mode input voltage at ground potential. The input stage also allows differential input voltages up to 44 V, provided the maximum input voltage range is not exceeded. Specifically, the input voltages must range between VEE and VCC supply voltages as shown by the maximum rating table. In practice, although not recommended, the input voltages can exceed the VCC voltage by approximately 3.0 V and decrease below the VEE voltage by 0.3 V without causing product damage, although output phase reversal may occur. It is also possible to source up to approximately 5.0 mA of current from VEE through either inputs clamping diode without damage or latching, although phase reversal may again occur. If one or both inputs exceed the upper common mode voltage limit, the amplifier output is readily predictable and may be in a low or high state depending on the existing input bias conditions. Since the input capacitance associated with the small geometry input device is substantially lower (2.5 pF) than the typical JFET input gate capacitance (5.0 pF), better frequency response for a given input source resistance can be achieved using the MC34071 series of amplifiers. This performance feature becomes evident, for example, in fast settling D-to-A current to voltage conversion applications where the feedback resistance can form an input pole with the input capacitance of the op amp. This input pole creates a 2nd order system with the single pole op amp and is therefore detrimental to its settling time. In this context, lower input capacitance is desirable especially for higher
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MC34071,2,4,A MC33071,2,4,A
values of feedback resistances (lower current DACs). This input pole can be compensated for by creating a feedback zero with a capacitance across the feedback resistance, if necessary, to reduce overshoot. For 2.0 kW of feedback resistance, the MC34071 series can settle to within 1/2 LSB of 8-bits in 1.0 ms, and within 1/2 LSB of 12-bits in 2.2 ms for a 10 V step. In a inverting unity gain fast settling configuration, the symmetrical slew rate is 13 V/ms. In the classic noninverting unity gain configuration, the output positive slew rate is +10 V/ms, and the corresponding negative slew rate will exceed the positive slew rate as a function of the fall time of the input waveform. Since the bipolar input device matching characteristics are superior to that of JFETs, a low untrimmed maximum offset voltage of 3.0 mV prime and 5.0 mV downgrade can be economically offered with high frequency performance characteristics. This combination is ideal for low cost precision, high speed quad op amp applications. The all NPN output stage, shown in its basic form on the equivalent circuit schematic, offers unique advantages over the more conventional NPN/PNP transistor Class AB output stage. A 10 kW load resistance can swing within 1.0 V of the positive rail (VCC), and within 0.3 V of the negative rail (VEE), providing a 28.7 Vpp swing from 15 V supplies. This large output swing becomes most noticeable at lower supply voltages. The positive swing is limited by the saturation voltage of the current source transistor Q7, and VBE of the NPN pull up transistor Q17, and the voltage drop associated with the short circuit resistance, R7. The negative swing is limited by the saturation voltage of the pull-down transistor Q16, the voltage drop ILR6, and the voltage drop associated with resistance R7, where IL is the sink load current. For small valued sink currents, the above voltage drops are negligible, allowing the negative swing voltage to approach within millivolts of VEE. For large valued sink currents (>5.0 mA), diode D3 clamps the voltage across R6, thus limiting the negative swing to the saturation voltage of Q16, plus the forward diode drop of D3 (VEE +1.0 V). Thus for a given supply voltage, unprecedented peak-to-peak output voltage swing is possible as indicated by the output swing specifications. If the load resistance is referenced to VCC instead of ground for single supply applications, the maximum possible output swing can be achieved for a given supply voltage. For light load currents, the load resistance will pull the output to VCC during the positive swing and the output will pull the load resistance near ground during the negative swing. The load resistance value should be much less than that of the feedback resistance to maximize pull up capability. Because the PNP output emitter-follower transistor has been eliminated, the MC34071 series offers a 20 mA minimum current sink capability, typically to an output voltage of (VEE +1.8 V). In single supply applications the output can directly source or sink base current from a common emitter NPN transistor for fast high current switching applications. In addition, the all NPN transistor output stage is inherently fast, contributing to the bipolar amplifier's high gain bandwidth product and fast settling capability. The associated high frequency low output impedance (30 W typ @ 1.0 MHz) allows capacitive drive capability from 0 pF to 10,000 pF without oscillation in the unity closed loop gain configuration. The 60 phase margin and 12 dB gain margin as well as the general gain and phase characteristics are virtually independent of the source/sink output swing conditions. This allows easier system phase compensation, since output swing will not be a phase consideration. The high frequency characteristics of the MC34071 series also allow excellent high frequency active filter capability, especially for low voltage single supply applications. Although the single supply specifications is defined at 5.0 V, these amplifiers are functional to 3.0 V @ 25C although slight changes in parametrics such as bandwidth, slew rate, and DC gain may occur. If power to this integrated circuit is applied in reverse polarity or if the IC is installed backwards in a socket, large unlimited current surges will occur through the device that may result in device destruction. Special static precautions are not necessary for these bipolar amplifiers since there are no MOS transistors on the die. As with most high frequency amplifiers, proper lead dress, component placement, and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted input-output coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input pole for optimum frequency response, but also minimizes extraneous "pick up" at this node. Supply decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. The output of any one amplifier is current limited and thus protected from a direct short to ground. However, under such conditions, it is important not to allow the device to exceed the maximum junction temperature rating. Typically for 15 V supplies, any one output can be shorted continuously to ground without exceeding the maximum temperature rating.
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MC34071,2,4,A MC33071,2,4,A
(Typical Single Supply Applications VCC = 5.0 V)
VCC 5.1 M VO 0 3.7 Vpp VCC 20 k Cin 1.0 M +
MC34071
0
3.7 Vpp
100 k CO VO 68 k Cin 100 k 10 k RL AV = 101 BW (-3.0 dB) = 45 kHz 10 k
36.6 mVpp Vin 1.0 k
+
MC34071
-
-
CO
VO 10 k RL
Vin 370 mVpp
100 k
AV = 10 BW (-3.0 dB) = 450 kHz
Figure 38. AC Coupled Noninverting Amplifier
Figure 39. AC Coupled Inverting Amplifier
VO 2.63 V
4.75 Vpp 91 k
VCC
5.1 k RL 5.1 k 100 k +
MC34071
2.5 V VO 0 1.0 M Vin +
MC34071
-
0 to 10,000 pF
MC54/74XX
- Vin AV = 10 BW (-3.0 dB) = 450 kHz
Cable
TTL Gate
Figure 40. DC Coupled Inverting Amplifier Maximum Output Swing
Figure 41. Unity Gain Buffer TTL Driver
R1 Vin Vin 0.2 Vdc R Vin 16 k C 0.01 R 16 k 1.1 k R2 5.6 k
C 0.047 C 0.047
R3 2.2 k -
MC34071
+
VO fo = 30 kHz Ho = 10 Ho = 1.0
VCC
-
MC34071
VO Given fo = Center Frequency AO = Gain at Center Frequency Choose Value fo, Q, Ao, C Then: fo = 1.0 kHz fo = 1 4pRC R3 = Q R3 R1 = pfoC 2Ho
0.4 VCC
+
R2 =
32 k
2.0 R
R1 R3 4Q2R1-R3 Qofo GBW < 0.1
For less than 10% error from operational amplifier where fo and GBW are expressed in Hz. GBW = 4.5 MHz Typ.
2.0 C 0.02
2.0 C 0.02
Figure 42. Active High-Q Notch Filter http://onsemi.com
12
Figure 43. Active Bandpass Filter
MC34071,2,4,A MC33071,2,4,A
CF 2.0 V RF 5.0 k 5.0 k 5.0 k -
MC34071
Vin
Vin VO VCC
+
MC34071
VO t VO 4.0 V 13 V/ms 0.2 ms Delay 25 V/ms t Delay 1.0 ms 2.0 k RL
-
10 k Bit Switches
10 k
10 k
+
1.0 V
(R-2R) Ladder Network Settling Time 1.0 ms (8-Bits, 1/2 LSB)
0.1
Figure 44. Low Voltage Fast D/A Converter
Figure 45. High Speed Low Voltage Comparator
VCC ON" Vin < Vref VCC Vin Vref ON" Vin > Vref (A) PNP +
MC34071
VCC
RL +
MC34071
-
+
MC34071
- RL
-
(B) NPN
Figure 46. LED Driver
Figure 47. Transistor Driver
ILoad
+
MC34071
RF VO ICell R1 R1 R2 VCell = 0 V VO = ICell RF VO > 0.1 V -
MC34071
- Ground Current Sense Resistor RS
VO
+ 1+
R2
VO = ILoad RS
For VO > 0.1V BW ( -3.0 dB) = GBW R2 R1+R2
Figure 48. AC/DC Ground Current Monitor
Figure 49. Photovoltaic Cell Amplifier
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MC34071,2,4,A MC33071,2,4,A
VO R2 Vref R1 VOH +
MC34071
Hysteresis
Iout Vin VinL VinH Vref Vin +
MC34071
- Vin VinL = VinH = VH = R1 (VOL-Vref)+Vref R1+R2 R1 (VOH-Vref)+Vref R1+R2 R1 (VOH -VOL) R1+R
VOL
-
Iout =
VinVIO R
R
Figure 50. Low Input Voltage Comparator with Hysteresis
Figure 51. High Compliance Voltage to Sink Current Converter
R1
R2 R4 - 1/2 R3 - 1/2 MC34072 + VO R +Vref RF R -
MC34071
MC34072
+V1 +V2
+
VO
R = DR
R
+ DR RF 2R2
R2 R4 = (Critical to CMRR) R1 R3 R4 R4 VO = 1 + V2-V1 R3 R3 For (V2 V1), V > 0
DR < < R RF > > R
RF
VO = Vref
(VO 0.1 V)
Figure 52. High Input Impedance Differential Amplifier
fOSC ^
Figure 53. Bridge Current Amplifier
0.85 RC V VP + IB 0 - + ISC t Base Charge Removal Iout - 1/2 R + 1/2 MC34072 - 100 k 100 k 47 k VP Pulse Width Control Group
Vin +
MC34071
VO = Vin (pk)
t
-
+ RL VP 10,000 pF V+ Vin VP C
MC34072
+
IB
OSC t
Comparator
High Current Output
Figure 54. Low Voltage Peak Detector
Figure 55. High Frequency Pulse Width Modulation
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MC34071,2,4,A MC33071,2,4,A
GENERAL ADDITIONAL APPLICATIONS INFORMATION VS = 15.0 V
C2 0.02 R1 560 R3 510 R2 5.6 k -
MC34071
C2 0.05
C1 1.0
R1 46.1 k -
C1 1.0 fo = 1.0 kHz Ho = 10
MC34071
R2 1.1 k
+
fo = 100 Hz Ho = 20 Ho+0.5 pfoC1 2 2 2pfoC1 (1/Ho+2) C Ho
C1 0.44
+
Choose: fo, Ho, C1
Then: R1 = R2 = C2 =
Choose: fo, Ho, C2 Then: C1 = 2C2 (Ho+1) R2 = 2 4pfoC2 R3 = R2 Ho+1 R1 = R2 Ho
Figure 56. Second Order Low-Pass Active Filter
Figure 57. Second Order High-Pass Active Filter
CF* RF 2.0 k + VO Vin R1
MC34071
VO = 10 V Step
-
MC34071
VO RL
+ I Uncompensated High Speed DAC *Optional Compensation Compensated ts = 1.0 ms to 1/2 LSB (8-Bits) ts = 2.2 ms to 1/2 LSB (12-Bits) SR = 13 V/ms
- R2
VO Vin
=
R2 BW (-3.0 dB) = GBW R1
R1 R1 +R2
SR = 13 V/ms
Figure 58. Fast Settling Inverter
Figure 59. Basic Inverting Amplifier
+
MC34071
VO +
MC34071
- Vin R2 RL R1 Vin VO
- VO Vin R2 R1 R1 R1 +R2 BWp = 200 kHz VO = 20 Vpp SR = 10 V/ms
=
1+
BW (-3.0 dB) = GBW
Figure 60. Basic Noninverting Amplifier
Figure 61. Unity Gain Buffer (AV = +1.0)
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MC34071,2,4,A MC33071,2,4,A
+
MC34074
R
R
- R - RE R
MC34074
VO
+
-
MC34074
R
+
R
Example: Let: R = RE = 12 k Then: AV = 3.0 BW = 1.5 MHz
AV = 1 + 2
R RE
Figure 62. High Impedance Differential Amplifier
+VO
+ 100 k +10 -
MC34074 MC34074
+ 10 10
+ RL
-
220 pF
+ 100 k -10 + + + 10 -VO 10 RL
RL
+VO 18.93 18 15.4
-VO -18.78 -18 -15.4
10 k 5.0 k
100 k
MC34074
-
Figure 63. Dual Voltage Doubler
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MC34071,2,4,A MC33071,2,4,A
ORDERING INFORMATION
Op Amp Function MC34071P MC34071AP Single MC34071D MC34071AD MC34071DR2 MC34071ADR2 MC34072P MC34072PG MC34072AP MC34072D MC34072DG MC34072AD MC34072DR2 MC34072DR2G MC34072ADR2 Dual MC34072ADR2G MC33072P MC33072PG MC33072AP MC33072D MC33072AD MC33072DR2 MC33072DR2G MC33072ADR2 MC34072VD MC34072VDR2 MC34072VP MC34074P MC34074AP MC34074D MC34074AD MC34074DR2 MC34074DR2G MC34074ADR2 MC33074P MC33074AP MC33074D, MC33074AD MC33074DR2 MC33074ADR2 MC33074DTB MC33074ADTB TA = -40 to +85C TA = 0 to +70C TA = -40 to +125C 0o 5C TA = -40 to +85C 40 TA = 0 to +70C TA = 0 to +70C Device Operating Temperature Range Package PDIP-8 PDIP-8 SOIC-8 SOIC-8 SOIC-8 SOIC-8 PDIP-8 PDIP-8 (Pb-Free) PDIP-8 SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 (Pb-Free) PDIP-8 PDIP-8 (Pb-Free) PDIP-8 SOIC-8 SOIC-8 SOIC-8 SOIC-8 (Pb-Free) SOIC-8 SOIC-8 SOIC-8 PDIP-8 PDIP-14 PDIP-14 SOIC-14 SOIC-14 SOIC-14 SOIC-14 (Pb-Free) SOIC-14 PDIP-14 PDIP-14 SOIC-14 SOIC-14 SOIC-14 TSSOP-14 (Pb-Free) TSSOP-14 (Pb-Free) Shipping 50 Units / Rail 50 Units / Rail 98 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 50 Units / Rail 50 Units / Rail 50 Units / Rail 98 Units / Rail 98 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 2500 Units / Tape & Reel 2500 Units / Tape & Reel 1000 Units / Rail 1000 Units / Tube 50 Units / Rail 98 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 2500 Units / Tape & Reel 98 Units / Rail 2500 Units / Tape & Reel 50 Units / Rail 25 Units / Rail 25 Units / Rail 55 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 2500 Units / Tape & Reel 25 Units / Rail 25 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 96 Units / Rail 96 Units / Rail
Quad
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MC34071,2,4,A MC33071,2,4,A
Op Amp Function Operating Temperature Range Shipping 2500 Units / Tape & Reel 2500 Units / Tape & Reel 55 Units / Rail 55 Units / Rail 2500 Units / Tape & Reel 25 Units / Rail
Device MC33074DTBR2 MC33074ADTBR2
Package TSSOP-14 (Pb-Free)
TA = -40 to +85C 40
TSSOP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 PDIP-14
Quad
MC34074VD MC34074VDG TA = -40 to +125C 40 +125 C MC34074VDR2 MC34074VP
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
PPDIP-8 P SUFFIX CASE 626 8 MC3x071P AWL YYWW 1 1 8 MC3x071AP AWL YYWW 1 SOIC-8 D SUFFIX CASE 751 8 3x071 ALYW 1 1 8 3x071 ALYWA 1 8 3x072 ALYW 1 8 3x072 ALYWA 1 8 3x072 ALYWV 8 MC3x072P AWL YYWW 1 8 MC3x072AP AWL YYWW 1 8 MC34072VP AWL YYWW
PPDIP-14 P SUFFIX CASE 646 14 MC3x074P AWLYYWW 1 SOIC-14 D SUFFIX CASE 751A 14 MC3x074D AWLYWW 1 1 14 MC3x074AD AWLYWW 1 1 x = 3 or 4 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week 14 MC34074VD AWLYWW 14 MC33 074 ALYW 1 1 14 MC3x074AP AWLYYWW 1 TSSOP-14 DTB SUFFIX CASE 948G 14 MC33 074A ALYW 14 MC34074VP AWLYYWW
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MC34071,2,4,A MC33071,2,4,A
PACKAGE DIMENSIONS
PDIP-8 P SUFFIX CASE 626-05 ISSUE L
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040
8
5
-B-
1 4
F
NOTE 2
-A- L
C -T-
SEATING PLANE
J N D K
M
M
H
G 0.13 (0.005) TA
M
B
M
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MC34071,2,4,A MC33071,2,4,A
PACKAGE DIMENSIONS
SOIC-8 D SUFFIX CASE 751-07 ISSUE AB
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060 7.0 0.275 4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC34071,2,4,A MC33071,2,4,A
PACKAGE DIMENSIONS
PDIP-14 P SUFFIX CASE 646-06 ISSUE M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01
14
8
B
1 7
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
DIM A B C D F G H J K L M N
SOIC-14 D SUFFIX CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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MC34071,2,4,A MC33071,2,4,A
PACKAGE DIMENSIONS
TSSOP-14 DTB SUFFIX CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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EE CC EE CC
MC34071/D

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